1. Field of the Invention
This invention generally relates to computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout. Certain embodiments relate to a computer-implemented method for creating a metrology target structure design for a reticle layout that includes simulating how one or more initial metrology target structures will be formed on a wafer and simulating one or more spectra that will be produced by a predetermined metrology system configuration for each of the simulated one or more initial metrology target structures.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
As the dimensions of advanced semiconductor devices continue to shrink, process control windows are shrinking commensurately. Accordingly, monitor and control of semiconductor processes are and will continue to be of significant importance in semiconductor development and manufacturing. Consequently, significant efforts have been and will continue to be made to improve the target structures that can be measured and used to monitor and control semiconductor fabrication processes.
Currently, metrology engineers work with graphical data stream (GDS) metrology target libraries or collaborate with layout engineers to modify generic target designs based on known rules of thumb in order to make a best effort to design metrology target structures that are compatible with lithographic design rules, process constraints, and metrology performance considerations. Another common methodology for metrology target structure optimization includes printing several different metrology target structure designs side by side on a wafer. Optimization may be performed for the device itself, and then the best target of the several that were printed may be selected for use for fabrication of the device.
There are, however, a number of disadvantages to creating the metrology target structures as described above. For instance, such creation of metrology target structures is substantially time consuming. In particular, the trial and error nature of such approaches to metrology structure design take a relatively long time. Creating the metrology structures in this manner can also sometimes take up to three mask design iterations until the design is satisfactory. In addition, such creation of metrology structures requires technical input from a number of different domain experts who may not always be available to support the metrology engineer. Furthermore, creating metrology structures in such a manner can result in target designs that are suboptimal in at least one of the three areas that include lithography compatibility, process compatibility, and metrology compatibility. Moreover, the methods described above, which involve printing several different metrology target structure designs side by side on a wafer, are cumbersome since these methods require particular optimization of the metrology targets instead of allowing optimization to be concentrated on the device printing and processing.
Accordingly, it would be advantageous to develop computer-implemented methods, carrier media, and/or systems for creating a metrology target structure design for a reticle layout that reduces the number of design cycles involved in the design process and automates the design process therefore reducing the work load and level of expertise required of the metrology engineer to perform target design and insertion into test and/or product reticles.